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| P3C1024 HIGH SPEED 128K x 8 3.3V STATIC CMOS RAM FEATURES 3.3 Volts Power Supply High Speed (Equal Access and Cycle Times) -- 15/17/20/25/35 ns (Commercial) -- 20/25/35/45 ns (Industrial) Single 3.3 Volts 0.3 Volts Power Supply Easy Memory Expansion Using CE2 and 1, Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast tOE Automatic Power Down Packages --32-Pin DIP and SOJ DESCRIPTION The P3C1024 is a 1,048,576-bit high-speed CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 3.3V 0.3V tolerance power supply. The P3C1024 device provides asynchronous operations with matching access and cycle times. Memory locations are specified on address pins A0 to A16. Reading is accomplished by device selection ( 1 low and CE2 high) and output enabling ( ) while write enable ( ) remains HIGH. By presenting the address under these conditions, the data in the addressed memory Access times of 20 nanoseconds permit greatly en- location is presented on the data input/output pins. The hanced system operating speeds. CMOS is utilized to input/output pins stay in the HIGH Z state when either reduce power consumption to a low level. The P3C1024 or is HIGH or or CE2 is LOW. 1 is a member of a family of PACE RAMTM products offering fast access times. Package options for the P3C1024 include 32-pin 300 mil DIP and SOJ packages as well as 400 mil SOJ. FUNCTIONAL BLOCK DIAGRAM A (9) A 262,144BIT MEMORY ARRAY PIN CONFIGURATION NC A16 A14 A12 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 1024.2 I/O1 INPUT DATA CONTROL COLUMN I/O A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 I/O2 COLUMN SELECT WE CE1 CE2 OE CONTROL CIRCUIT A *** *** GND A 1024.1 (8) DIP , SOJ TOP VIEW Means Quality, Service and Speed 1Q97 159 160 |
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